Hugging Peers

Lars Braun

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20 papers 2004–2011

Dynamic Processor Reconfiguration

Michael Hübner, Carsten Tradowsky, Diana Göhringer, Lars Braun, Florian Thoma, Jörg Henkel
+1 more show fewer
Jürgen Becker
2011-01 ReConFig

Intrinsic Identification of Xilinx Virtex-5 FPGA Devices Using Uninitialized Parts of Configuration Memory Space

Oliver Sander, Benjamin Glas, Lars Braun, Klaus D. Müller-Glaser, Jürgen Becker
2010-01 ReConFig

An adaptive and scalable multiprocessor system For Xilinx FPGAs using minimal sized processor cores

Alexander Klimm, Lars Braun, Jürgen Becker
2008-01 IPDPS

Run-time reconfigurable adaptive multilayer network-on-chip for FPGA-based systems

Michael Hübner, Lars Braun, Diana Göhringer, Jürgen Becker
2008-01 IPDPS

Data reallocation by exploiting FPGA configuration mechanisms

Oliver Sander, Lars Braun, Michael Hübner, Jürgen Becker
2008-01 ARC

FPGA Analysis Tool: High-Level Flows for Low-Level Design Analysis in Reconfigurable Computing

Krzysztof Kepa, Fearghal Morgan, Krzysztof Kosciuszkiewicz, Lars Braun, Michael Hübner, Jürgen Becker
2009-01 ARC

A FPGA based fast runtime reconfigurable real-time Multi-Object-Tracker

Matthias Rümmele-Werner, Thomas Perschke, Lars Braun, Michael Hübner, Jürgen Becker
2011-01 ISCAS

Data path driven waveform-like reconfiguration

Lars Braun, Katarina Paulsson, Herrmann Krömer, Michael Hübner, Jürgen Becker
2008-01 FPL

Scalable Application-Dependent Network on Chip Adaptivity for Dynamical Reconfigurable Real-Time Systems

Michael Hübner, Michael Ullmann, Lars Braun, A. Klausmann, Jürgen Becker
2004-01 FPL

Fine grain reconfigurable architectures

Josef Angermeier, Mateusz Majer, Jürgen Teich, Lars Braun, Tobias Schwalb, Philipp Graf
+9 more show fewer
Michael Hübner, Jürgen Becker, Enno Lübbers, Marco Platzner, Christopher Claus, Walter Stechele, Andreas Herkersdorf, Markus Rullmann, Renate Merker
2008-01 FPL

A multi-platform controller allowing for maximum Dynamic Partial Reconfiguration throughput

Christopher Claus, Bin Zhang, Walter Stechele, Lars Braun, Michael Hübner, Jürgen Becker
2008-01 FPL

Circuit Switched Run-Time Adaptive Network-on-Chip for Image Processing Applications

Lars Braun, Michael Hübner, Jürgen Becker, Thomas Perschke, Volker Schatz, Stefan Bach
2007-01 FPL

Run-time resource instantiation for fault tolerance in FPGAs

Monica Magalhães Pereira, Lars Braun, Michael Hübner, Jürgen Becker, Luigi Carro
2011-01 AHS

Fast Start-up for Spartan-6 FPGAs using Dynamic Partial Reconfiguration

Joachim Meyer, Juanjo Noguera, Michael Hübner, Lars Braun, Oliver Sander, R. M. Gil
+2 more show fewer
Rodney Stewart, Jürgen Becker
2011-01 DATE

Development of a method for image-based motion estimation of a VTOL-MAV on FPGA

Natalie Frietsch, I. Pashkovskiy, Gert F. Trommer, Lars Braun, Matthias Birk, Michael Hübner
+1 more show fewer
Jürgen Becker
2011-01 DASIP

Fast Sequential FPGA Startup Based on Partial and Dynamic Reconfiguration

Michael Hübner, Joachim Meyer, Oliver Sander, Lars Braun, Jürgen Becker, Juanjo Noguera
+1 more show fewer
Rodney Stewart
2010-01 ISVLSI

Physical Configuration On-Line Visualization of Xilinx Virtex-II FPGAs

Michael Hübner, Lars Braun, Jürgen Becker, Christopher Claus, Walter Stechele
2007-01 ISVLSI

FPGA Startup Through Sequential Partial and Dynamic Reconfiguration

Joachim Meyer, Michael Hübner, Lars Braun, Oliver Sander, Juanjo Noguera, Rodney Stewart
+1 more show fewer
Jürgen Becker
2010-01 ISVLSI (Selected papers)