Marc Belleville
18 papers 2007–2015
Multi-application electrical stimulator architecture dedicated to waveform control by electrode-tissue impedance spectra monitoring
2012-01
ICECS
Digital Timing Slack Monitors and Their Specific Insertion Flow for Adaptive Compensation of Variabilities
2009-01
PATMOS
Experimental analysis of flip-flops minimum operating voltage in 28nm FDSOI and the impact of back bias and temperature
2014-01
PATMOS
Dedicated network for distributed configuration in a mixed-signal Wireless Sensor Node circuit
2015-01
PATMOS
An On-Chip Multi-mode Buck DC-DC Converter for Fine-Grain DVS on a Multi-power Domain SoC Using a 65-nm Standard CMOS Logic Process
2009-01
PATMOS
A mixed LPDDR2 impedance calibration technique exploiting 28nm Fully-Depleted SOI Back-Biasing
2012-01
ICICDT
A CBRAM-based compact interconnect switch for non-volatile reconfigurable logic circuits
2013-01
ICICDT
An efficient metric of setup time for pulsed flip-flops based on output transition time
2013-01
ICICDT
A gate level methodology for efficient statistical leakage estimation in complex 32nm circuits
2013-01
DATE
Power-Clock Generator Impact on the Performance of NEM-Based Quasi-Adiabatic Logic Circuits
2015-01
RC