Hugging Peers

Muhammad M. Khellah

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42 papers 1998–2023

Adaptive clocking with dynamic power gating for mitigating energy efficiency & performance impacts of fast voltage droop in a 22nm graphics execution core

Minki Cho, Carlos Tokunaga, Stephen T. Kim, James W. Tschanz, Muhammad M. Khellah, Vivek De
2016-01 VLSI Circuits

A 0.05pJ/Pixel 70fps FHD 1Meps Event-Driven Visual Data Processing Unit

Somnath Paul, Turbo Majumder, Charles Augustine, Andres F. Malavasi, S. Usirikayala, Raghavan Kumar
+9 more show fewer
Jisna Kollikunnel, S. Chhabra, Satish Yada, M. L. Barajas, Carlos Ornelas, Dan Lake, Muhammad M. Khellah, Jim Tschanz, Vivek De
2020-01 VLSI Circuits

2X-Bandwidth Burst 6T-SRAM for Memory Bandwidth Limited Workloads

Charles Augustine, Somnath Paul, Turbo Majumder, James W. Tschanz, Muhammad M. Khellah, Vivek De
2020-01 VLSI Circuits

All-Digital Closed-Loop Unified Retention/Wake-Up Clamp in a 10nm 4-Core x86 IP

Charles Augustine, A. Afzal, U. Misgar, Abdullah A. Owahid, A. Raman, K. Subramanian
+3 more show fewer
Feroze Merchant, James W. Tschanz, Muhammad M. Khellah
2021-01 VLSI Circuits

Low Swing and Column Multiplexed Bitline Techniques for Low-Vmin, Noise-Tolerant, High-Density, 1R1W 8T-Bitcell SRAM in 10nm FinFET CMOS

Jaydeep P. Kulkarni, Andres Malavasi, Charles Augustine, Carlos Tokunaga, Jim Tschanz, Muhammad M. Khellah
+1 more show fewer
Vivek De
2020-01 VLSI Circuits

An All-Digital, VMAX-Compliant, and Stable Distributed Charge Injection Scheme for Fast Mitigation of Voltage Droop

Suyoung Bang, Minki Cho, Pascal Meinerzhagen, Andres Malavasi, Muhammad M. Khellah, James W. Tschanz
+1 more show fewer
Vivek De
2019-01 ESSCIRC

Min-Delay Margin/Error Detection and Correction for Flip-Flops and Pulsed Latches in 10-nm CMOS

Pascal Andreas Meinerzhagen, Sandip Kundu, Andres Malavasi, Trang Nguyen, Muhammad M. Khellah, James W. Tschanz
+1 more show fewer
Vivek De
2019-01 ESSCIRC

Time-borrowing multi-cycle on-chip interconnects for delay variation tolerance

Keith A. Bowman, James W. Tschanz, Muhammad M. Khellah, Maged Ghoneima, Yehea I. Ismail, Vivek De
2006-01 ISLPED

Resilient microprocessor design for high performance & energy efficiency

Keith A. Bowman, James W. Tschanz, Shih-Lien Lu, Paolo A. Aseron, Muhammad M. Khellah, Arijit Raychowdhury
+5 more show fewer
Bibiche M. Geuskens, Carlos Tokunaga, Chris Wilkerson, Tanay Karnik, Vivek De
2010-01 ISLPED

Serial-link bus: a low-power on-chip bus architecture

Maged Ghoneima, Yehea I. Ismail, Muhammad M. Khellah, James W. Tschanz, Vivek De
2005-01 ICCAD

Effective Capacitance Macro-Modelling for Architectural-Level Power Estimation

Muhammad M. Khellah, Mohamed I. Elmasry
1998-01 Great Lakes Symposium on VLSI

A Low-Power High-Performance Embedded SRAM Macrocell

Amr M. Fahim, Muhammad M. Khellah, Mohamed I. Elmasry
1998-01 Great Lakes Symposium on VLSI

A 2.6 mV/b Resolution, 1.2 GHz Throughput, All-Digital Voltage Droop Monitor Using Coupled Ring Oscillators in Intel 4 CMOS

Charles Augustine, Pascal Meinerzhagen, Wootaek Lim, A. Veerabathini, M. Bright, K. Mojjada
+3 more show fewer
Jim Tschanz, Muhammad M. Khellah, Vivek De
2023-01 VLSI Technology and Circuits

Reducing the data switching activity of serialized datastreams

Maged Ghoneima, Yehea I. Ismail, Muhammad M. Khellah, Vivek De
2006-01 ISCAS

Skewing adjacent line repeaters to reduce the delay and energy dissipation of on-chip buses

Yehea I. Ismail, Muhammad M. Khellah, Maged Ghoneima, James W. Tschanz, Yibin Ye, Vivek De
2005-01 ISCAS (1)

Synaptic sampling in hardware spiking neural networks

Sadique Sheik, Somnath Paul, Charles Augustine, Chinnikrishna Kothapalli, Muhammad M. Khellah, Gert Cauwenberghs
+1 more show fewer
Emre Neftci
2016-01 ISCAS

Evaluation of differential vs. single-ended sensing and asymmetric cells in 90 nm logic technology for on-chip caches

Yibin Ye, Muhammad M. Khellah, Dinesh Somasekhar, Vivek De
2006-01 ISCAS

Trading off Cache Capacity for Reliability to Enable Low Voltage Operation

Chris Wilkerson, Hongliang Gao, Alaa R. Alameldeen, Zeshan Chishti, Muhammad M. Khellah, Shih-Lien Lu
2008-01 ISCA