Xiaochen Hao

Systolic Computing on GPUs for Productive Performance

We propose a language and compiler to productively build high-performance {\it software systolic arrays} that run on GPUs. Based on a rigorous mathematical foundation (uniform recurrence equations...

Research of inter-cluster multi-hop routing algorithm for wireless sensor networks

Degree-optimized LMPT topology control algorithm of wireless sensor networks

A Mapping Model of SNNs to Neuromorphic Hardware

Process fault detection of cement calcination system based on median filtered DPCA

MatFactory: A Framework for High-Performance Matrix Factorization on FPGAs

Monad: Towards Cost-Effective Specialization for Chiplet-Based Spatial Accelerators

Hierarchical Power Co-Optimization and Management for LLM Chiplet Designs

Telos: A Dataflow Accelerator for Sparse Triangular Solver of Partial Differential Equations

Lasa: Abstraction and Specialization for Productive and Performant Linear Algebra on FPGAs

Integrating Cyber-Attack Defense Techniques into Real-Time Cyber-Physical Systems

POPA: Expressing High and Portable Performance across Spatial and Vector Architectures for Tensor Computations

StructILU: Dependency-Preserving Incomplete LU with Hierarchical Parallelism for Structured Grid PDEs on GPUs

A Unified Synthesis Framework for Dataflow Accelerators Through Multi-level Software and Hardware Intermediate Representations

Monad: Towards Cost-effective Specialization for Chiplet-based Spatial Accelerators

Advanced packaging offers a new design paradigm in the post-Moore era, where many small chiplets can be assembled into a large system. Based on heterogeneous integration, a chiplet-based...