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Carsten Tradowsky

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15 papers 2011–2017

Determination of on-chip temperature gradients on reconfigurable hardware

Carsten Tradowsky, Enrique Cordero, Thorsten Deuser, Michael Hübner, Jürgen Becker
2012-01 ReConFig

Dynamic Processor Reconfiguration

Michael Hübner, Carsten Tradowsky, Diana Göhringer, Lars Braun, Florian Thoma, Jörg Henkel
+1 more show fewer
Jürgen Becker
2011-01 ReConFig

On Dynamic Run-time Processor Pipeline Reconfiguration

Carsten Tradowsky, Florian Thoma, Michael Hübner, Jürgen Becker
2012-01 IPDPS Workshops

Adaptive processor architecture - invited paper

Michael Hübner, Diana Göhringer, Carsten Tradowsky, Jörg Henkel, Jürgen Becker
2012-01 ICSAMOS

A Dynamic Cache Architecture for Efficient Memory Resource Allocation in Many-Core Systems

Carsten Tradowsky, Enrique Cordero, Christoph Orsinger, Malte Vesper, Jürgen Becker
2016-01 ARC

Towards Dynamic Cache and Bandwidth Invasion

Carsten Tradowsky, Martin Schreiber, Malte Vesper, Ivan Domladovec, Maximilian Braun, Hans-Joachim Bungartz
+1 more show fewer
Jürgen Becker
2014-01 ARC

TEAChER: TEach AdvanCEd Reconfigurable Architectures and Tools

Kostas Siozios, Peter Figuli, Harry Sidiropoulos, Carsten Tradowsky, Dionysios Diamantopoulos, Konstantinos Maragos
+3 more show fewer
Shalina Percy Delicia, Dimitrios Soudris, Jürgen Becker
2015-01 ARC

A Novel Concept for Adaptive Signal Processing on Reconfigurable Hardware

Peter Figuli, Carsten Tradowsky, Jose Martinez, Harry Sidiropoulos, Kostas Siozios, Holger Stenschke
+2 more show fewer
Dimitrios Soudris, Jürgen Becker
2015-01 ARC

SmartLoCore: A Concept for an Adaptive Power-Aware Localization Processor

Carsten Tradowsky, Tobias Gädeke, Thomas Bruckschlögl, Wilhelm Stork, Klaus D. Müller-Glaser, Jürgen Becker
2014-01 PDP

Adaptive Cache Structures

Carsten Tradowsky, Enrique Cordero, Christoph Orsinger, Malte Vesper, Jürgen Becker
2016-01 ARCS

LISPARC: Using an architecture description language approach for modelling an adaptive processor microarchitecture

Carsten Tradowsky, Florian Thoma, Michael Hübner, Jürgen Becker
2012-01 SIES

ViSA: A highly efficient slot architecture enabling multi-objective ASIP cores

Peter Figuli, Carsten Tradowsky, Nadine Gaertner, Jürgen Becker
2013-01 ISSoC

Pegasus: Efficient data transfers for PGAS languages on non-cache-coherent many-cores

Manuel Mohr, Carsten Tradowsky
2017-01 DATE

Auto-SI: An adaptive reconfigurable processor with run-time loop detection and acceleration

Tanja Harbaum, Christoph Schade, Marvin Damschen, Carsten Tradowsky, Lars Bauer, Jörg Henkel
+1 more show fewer
Jürgen Becker
2017-01 SoCC

LImbiC: An adaptable architecture description language model for developing an application-specific image processor

Carsten Tradowsky, Tanja Harbaum, Shaver Deyerle, Jürgen Becker
2013-01 ISVLSI