A gate level methodology for efficient statistical leakage estimation in complex 32nm circuits

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Smriti Joshi,Anne Lombardot,Marc Belleville,Edith Beigné,Stéphane Girard

DATE

published 1st of January, 2013

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HuggingPeers ID: ID hpp-3bRYaQqLXRT
Publication: DATE
Published: 1st of January, 2013

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Source	ID	Citations
DBLP	conf/date/JoshiLBBG13	—

Cite this paper

@article{joshi2013,
  title = {A gate level methodology for efficient statistical leakage estimation in complex 32nm circuits},
  author = {Smriti Joshi and Anne Lombardot and Marc Belleville and Edith Beigné and Stéphane Girard},
  journal = {DATE},
  year = {2013},
  month = {Jan},
  doi = {10.7873/date.2013.221},
  url = {https://doi.org/10.7873/date.2013.221},
}

Smriti Joshi et al. (2013). A gate level methodology for efficient statistical leakage estimation in complex 32nm circuits. DATE. https://doi.org/10.7873/date.2013.221

Smriti Joshi, et al.. "A gate level methodology for efficient statistical leakage estimation in complex 32nm circuits." DATE, 2013, https://doi.org/10.7873/date.2013.221.

Smriti Joshi, et al.. "A gate level methodology for efficient statistical leakage estimation in complex 32nm circuits." DATE (2013). https://doi.org/10.7873/date.2013.221

Smriti Joshi et al., 2013. A gate level methodology for efficient statistical leakage estimation in complex 32nm circuits. DATE. Available at: <https://doi.org/10.7873/date.2013.221>.

TY  - JOUR
TI  - A gate level methodology for efficient statistical leakage estimation in complex 32nm circuits
AU  - Smriti Joshi
AU  - Anne Lombardot
AU  - Marc Belleville
AU  - Edith Beigné
AU  - Stéphane Girard
PY  - 2013
JO  - DATE
DO  - 10.7873/date.2013.221
UR  - https://doi.org/10.7873/date.2013.221
ER  -