Alan Mishchenko

Logic Synthesis Meets Machine Learning: Trading Exactness for Generalization

Logic synthesis is a fundamental step in hardware design whose goal is to find structural representations of Boolean functions while minimizing delay and area. If the function is...

Circuit-Based Intrinsic Methods to Detect Overfitting

The focus of this paper is on intrinsic methods to detect overfitting. By intrinsic methods, we mean methods that rely only on the model and the training data, as opposed to traditional methods...

A Single-Instance Incremental SAT Formulation of Proof- and Counterexample-Based Abstraction

This paper presents an efficient, combined formulation of two widely used abstraction methods for bit-level verification: counterexample-based abstraction (CBA) and proof-based abstraction (PBA)....

SAT-Based Complete Don't-Care Computation for Network Optimization

This paper describes an improved approach to Boolean network optimization using internal don't-cares. The improvements concern the type of don't-cares computed, their scope, and the computation...

Efficient Solution of Language Equations Using Partitioned Representations

A class of discrete event synthesis problems can be reduced to solving language equations f . X ⊆ S, where F is the fixed component and S the specification. Sequential synthesis deals with...

Reducing Multi-Valued Algebraic Operations to Binary

A Boolean Paradigm in Multi-Valued Logic Synthesis

Logic Synthesis of Reversible Wave Cascades

Encoding of Boolean Functions and its Application to LUT Cascade Synthesis

Topologically Constrained Logic Synthesis

Simplification of Non-Deterministic Multi-Valued Networks

Efficient SAT-based ATPG techniques for all multiple stuck-at faults

Automated Synthesis of Protocol Converters with BALM-II

Fast Boolean matching based on NPN classification

Improved carry chain mapping for the VTR flow

High Quality Circuit-Based 3-SAT Mappings for Oscillator Ising Machines

Logic synthesis and verification on fixed topology

SAT-Based Mapping of Data-Flow Graphs onto Coarse-Grained Reconfigurable Arrays