Fernando Moraes

Exploring NoC Mapping Strategies: An Energy and Timing Aware Technique

Complex applications implemented as Systems on Chip (SoCs) demand extensive use of system level modeling and validation. Their implementation gathers a large number of complex IP cores and...

MultiNoC: A Multiprocessing System Enabled by a Network on Chip

The MultiNoC system implements a programmable on-chip multiprocessing platform built on top of an efficient, low area overhead intra-chip interconnection scheme. The employed interconnection...

Wrapper Design for the Reuse of Networks-on-Chip as Test Access Mechanism

Adapting a C-element design flow for low power

Model-based design flow for NoC-based MPSoCs

A Cryptographic Coarse Grain Reconfigurable Architecture Robust Against DPA

Increasing NoC power estimation accuracy through a rate-based model

Evaluating the cost to cipher the NoC communication

Exploring Soft Error Susceptibility in FET Devices via Geant4 Simulation

Hermes-A - An Asynchronous NoC Router with Distributed Routing

QoS in Networks-on-Chip - Beyond Priority and Circuit Switching Techniques

Exploiting reconfigurability for low-power control of embedded processors

A monitored NoC with runtime path adaptation

Exploring the Impact of Soft Errors on NoC-based Multiprocessor Systems

A Heterogeneous and Distributed Co-Simulation Environment

Infrastructure for dynamic reconfigurable systems: choices and trade-offs

A high abstraction, high accuracy power estimation model for networks-on-chip

LASCA-Interconnect Parasitic Extraction Tool for Deep-Submicron IC Design