Architecture and Implementation of Power and Area Efficient Receiver Equalization Circuit for High-Speed Serial Data Communication

@article{song2006,
  title = {Architecture and Implementation of Power and Area Efficient Receiver Equalization Circuit for High-Speed Serial Data Communication},
  author = {Hongjiang Song},
  journal = {SoCC},
  year = {2006},
  month = {Jan},
  doi = {10.1109/socc.2006.283840},
  url = {https://doi.org/10.1109/socc.2006.283840},
}

Hongjiang Song (2006). Architecture and Implementation of Power and Area Efficient Receiver Equalization Circuit for High-Speed Serial Data Communication. SoCC. https://doi.org/10.1109/socc.2006.283840

Hongjiang Song. "Architecture and Implementation of Power and Area Efficient Receiver Equalization Circuit for High-Speed Serial Data Communication." SoCC, 2006, https://doi.org/10.1109/socc.2006.283840.

Hongjiang Song. "Architecture and Implementation of Power and Area Efficient Receiver Equalization Circuit for High-Speed Serial Data Communication." SoCC (2006). https://doi.org/10.1109/socc.2006.283840

Hongjiang Song, 2006. Architecture and Implementation of Power and Area Efficient Receiver Equalization Circuit for High-Speed Serial Data Communication. SoCC. Available at: <https://doi.org/10.1109/socc.2006.283840>.

TY  - JOUR
TI  - Architecture and Implementation of Power and Area Efficient Receiver Equalization Circuit for High-Speed Serial Data Communication
AU  - Hongjiang Song
PY  - 2006
JO  - SoCC
DO  - 10.1109/socc.2006.283840
UR  - https://doi.org/10.1109/socc.2006.283840
ER  -