Architecture and Implementation of Power and Area Efficient Receiver Equalization Circuit for High-Speed Serial Data Communication

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Hongjiang Song

SoCC

published 1st of January, 2006

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HuggingPeers ID: ID hpp-IRlrOCfHtgT
Publication: SoCC
Published: 1st of January, 2006

Provenance 1

Source	ID	Citations
DBLP	conf/socc/Song06a	—

Cite this paper

@article{song2006,
  title = {Architecture and Implementation of Power and Area Efficient Receiver Equalization Circuit for High-Speed Serial Data Communication},
  author = {Hongjiang Song},
  journal = {SoCC},
  year = {2006},
  month = {Jan},
  doi = {10.1109/socc.2006.283840},
  url = {https://doi.org/10.1109/socc.2006.283840},
}

Hongjiang Song (2006). Architecture and Implementation of Power and Area Efficient Receiver Equalization Circuit for High-Speed Serial Data Communication. SoCC. https://doi.org/10.1109/socc.2006.283840

Hongjiang Song. "Architecture and Implementation of Power and Area Efficient Receiver Equalization Circuit for High-Speed Serial Data Communication." SoCC, 2006, https://doi.org/10.1109/socc.2006.283840.

Hongjiang Song. "Architecture and Implementation of Power and Area Efficient Receiver Equalization Circuit for High-Speed Serial Data Communication." SoCC (2006). https://doi.org/10.1109/socc.2006.283840

Hongjiang Song, 2006. Architecture and Implementation of Power and Area Efficient Receiver Equalization Circuit for High-Speed Serial Data Communication. SoCC. Available at: <https://doi.org/10.1109/socc.2006.283840>.

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